Coreboot 25.12 significantly expands hardware support, including AMD Turin, new Intel motherboards, and laptops

  • Critical subsystems such as SMMSTORE, MIPI cameras, CFR for runtime configuration, and the Qualcomm X1P42100 platform are being reinforced.
  • Improvements to ACPI, APEI, commonlib and various drivers increase stability, error diagnostics and code consistency.
  • The project maintains its quarterly release cycle, with toolchains and vendor code updated and signed using GPG.
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coreboot 25.12

Coreboot has established itself as one of the most important open-source firmware projects for those who want Say goodbye to proprietary BIOS and enjoy a fast and transparent boot experience.The new coreboot version 25.12 It arrives as a stable quarterly release And it comes loaded with profound changes both at the hardware support level and internal infrastructure, geared towards OEMs, integrators and developers who need a solid foundation on which to build.

In this version have been integrated over 750 commits contributed by more than a hundred contributorsWith many new authors and a clear focus: expanding the number of supported platforms (especially Intel, AMD, Qualcomm and MediaTek), improving error handling through ACPI and APEI, strengthening MIPI camera management and SMMSTORE storage, and continuing to refine performance and stability details across the entire ecosystem.

Key new features of coreboot 25.12

The project announces coreboot 25.12 as the Latest version of the stable branch released in December within the quarterly cycleThis branch is primarily intended for manufacturers (OEM/ODM) and organizations that prefer a less dynamic base than the main branch. Even so, the developers themselves recommend that those compiling firmware for their own use work directly with the main branch, which is more up-to-date and receives continuous bug fixes.

Among the global changes, this version adds 757 commits, 106 authors, and 21 first-time contributing developersMore than 62.000 lines of code have been added and just under 10.000 have been removed, with a net difference of more than 52.000 lines, which makes it clear that this is not a simple minor revision, but a major leap in capabilities and platforms.

New platform and processor support in coreboot 25.12

One of the great strengths of coreboot 25.12 is the expansion of hardware support, with special attention to modern desktop and laptop ecosystem, servers and ARM devicesNew motherboards and new SoCs are being added, and several existing ones are being refined.

Preliminary support for AMD EPYC 9005 “Turin”

In the realm of x86_64 servers, coreboot 25.12 introduces a "proof of concept" level support for AMD EPYC 9005 processors, codenamed TurinThis is a first step that brings these processors closer to a completely open firmware, following the path already started with EPYC Genoa.

This preliminary support opens the door to the possibility that, in accordance openSIL matures to stable productionBoth EPYC and future generations of Ryzen and Zen 6 processors will have more motherboards compatible with open-source firmware. Currently, support is basic, but it points in the direction the community is moving towards, enabling next-generation servers to boot with Coreboot without relying on opaque firmware.

New motherboards and devices supported in coreboot 25.12

This version significantly extends the List of motherboards and systems with official support, ranging from classic hardware to the latest platforms. New features include:

  • ASRock Z77 Extreme4, geared towards 2nd and 3rd generation Intel Core processors, ideal for recycling old hardware with free firmware.
  • ASUS PRIME H610I-PLUS D4, a modern mini-ITX motherboard that supports 13th and 14th generation Intel Core processors, very interesting for today's compact systems.
  • Lenovo ThinkPad T470s and T580 (sklkbl_thinkpad variant), two very popular laptops in professional environments that add to the ecosystem of compatible laptops.
  • Siemens MC EHL6, within the Siemens MC EHL family, designed for industrial applications where firmware reliability is critical.
  • Star Labs Starfighter (Arrow Lake 285H), laptop geared towards users who are looking for a user-friendly device with open firmware from day one.
  • Topton ADL TWL (X2E_N150), a compact platform based on Alder Lake, typical of mini PCs and embedded systems.
  • Various Google ChromeOS devices: Fatcat (ruby), Ocelot (kodkod, ocicat), Rauru (Sapphire), Skywalker (Dooku, Grogu), which benefit from improvements in firmware configurations and drivers.

In addition to the list above, there continues to be a steady trickle of new Chromebooks and specific mainboard variantsThis is a common feature in every version of coreboot, which reinforces its presence in the educational and lightweight laptop ecosystem.

Qualcomm Snapdragon X1 Plus (X1P42100) and ARM ecosystem

In the ARM64 environment, coreboot 25.12 introduces the initial activation of the Qualcomm X1P42100 platform, known as Snapdragon X1 PlusThis step is key to bringing open firmware to SoCs designed for ARM laptops and always-connected devices.

The work on this SoC is not limited to "start it and that's it", but is accompanied by profound improvements in debugging and memory managementwhich we will see in more detail in a specific section, and which will lay the foundations for developers to be able to work comfortably on this platform throughout the device's life cycle.

Intel and AMD SoC Updates

Intel's coreboot adds support for LPCAMM (Low Power Compression Attached Memory Module) on Panther Lake platformsThis new type of memory module, designed for laptops and thin form factors, requires a particular topology that the firmware must know in order to detect and configure it correctly.

Infrastructure has been added to describe the LPCAMM topology Initial support for the Panther Lake RVP T3 reference board has also been added. This puts Coreboot ahead of the adoption of this memory technology in future generations of laptops.

At AMD, the platform Glinda receives numerous improvements and is expanded with the Faegan SoC variantKey changes include USB4 configuration via the FSP's device tree, the addition of 10GbE network devices, and accurate DIMM voltage communication within the FSP configuration. All of this translates into more refined and detailed support for modern AMD platforms.

Runtime configuration options (RFC)

One very visible improvement for manufacturers and advanced users is the extension of the runtime firmware configuration options, known as CFR or coreboot Forms RepresentationUntil now, many parameters required recompiling the image; with this framework, much of that configuration becomes dynamic.

A menu of options settings has been displayed in over 40 motherboards and variantsespecially within Google's ChromeOS ecosystem. These options allow, among other things:

  • Enable or disable Integrated GPU (iGPU).
  • Choose between touchpad and touch screen on hybrid devices.
  • Adjust parameters of fan control and certain hardware features.

The CFR framework defines for each option display name, help text, default value, and runtime flagsThis allows payloads (such as SeaBIOS, LinuxBoot, or others) to display a consistent menu. Furthermore, backward compatibility is maintained, and integration with UEFI variable storage and other persistent backends is planned.

Increased SMMSTORE capacity and associated improvements coming with coreboot 25.12

Another key element of this release is the change to the SMMSTORE protected storage subsystem. In coreboot 25.12, Doubles the default SMMSTORE size from 256 KB to 512 KBThis is important in systems that rely on UEFI variables and persistent data for advanced configurations.

Platforms like Sarien, Reef, Octopus, Drallion, Skyrim, Zork or GuybrushAmong other things, they have been updated to take advantage of this increase, ensuring reasonable space for current firmware variable demands.

Along with this leap in capacity, the following have been introduced Corrections to the alignment of the SMMSTORE v2 structureThis helps ensure consistent behavior across different architectures and payloads, minimizing surprises from subtle incompatibilities.

MIPI camera improvements for Intel platforms

MIPI camera management on Intel platforms, especially for operating systems like Windows, receives a major update. The MIPI camera driver now implements much more comprehensive SSDB (Sensor Static Data Block) support, with well-defined enums and bitfields for all relevant fields.

Most relevant improvements This area includes several changes aimed at the correct enumeration and configuration of sensors:

  • Systematic generation of the PLD (Physical Location Descriptor) information for each sensor, key for the system to know where each camera is physically located.
  • Automatic allocation of sensible default values ​​on the SSDBreducing the probability of incomplete configurations.
  • Improved support for VCM (Voice Coil Motor) type and I2C addresses, something fundamental for autofocus and other advanced functions.
  • Refactoring of Device Specific Method (DSM) methods into UUID-based functions, including new DSMs for Computer Vision Framework (CVF) and I2C V2.
  • Selection of ACPI device type and ROM configuration for camera sensors, with appropriate addresses.

This whole set of changes Improves camera enumeration and configuration in modern operating systemsavoiding common problems with recognition, orientation, and limited features in laptops and convertibles.

Qualcomm X1P42100 Platform: In-depth Debugging and Memory

Support for the Qualcomm X1P42100 SoC The Snapdragon X1 Plus is enhanced with a wide range of features geared towards development and problem-solving. Key new features include:

  • Download mode detection and ramdump packaging, facilitating the extraction of memory dumps in failure situations.
  • Support for upload ramdump images and packaging the APDP (Application Processor Debug Policy) image within CBFS, centralizing the debugging material in the firmware itself.
  • Improvements to the display subsystem: definition of MDSS registers for clock control, Lucidole PLL API, and proper DRAM allocation for video needs.
  • Settings in the memory design with relocation of the BL31 region and alignment of application memory in the secure environment (TZ), improving both security and RAM utilization.
  • Driver support CMD-DB (Command Database), which allows querying addresses and configurations of hardware accelerators, with the region mapped as non-cacheable in the MMU to avoid unwanted side effects.
  • Clear separation of the PRERAM and POSTRAM stacks in ARM64, moving the pre-main RAM stack to BSRAM and thereby optimizing the memory utilization and stability in the earliest stages of startup.

With all these tweaks, the X1P42100 platform becomes much more user-friendly for those who need diagnose faults, analyze memory dumps, and adjust SoC behavior in different production scenarios.

coreboot 25.12 introduces improvements in AMD: Glinda, Faegan and advanced ACPI

On the AMD side, in addition to the aforementioned expansion of the Glinda platform with the Faegan SoC, there is a significant set of changes focused on the ACPI integration quality and error managementAmong them we can highlight:

  • Report of fixed base addresses for the LPC bus, consistent with the specifications and the rest of the platform.
  • Support of I3C controllers at ACPI level, expanding communication capabilities with modern devices.
  • Incorporation of HEST (Hardware Error Source Table), key for the operating system to receive detailed information about hardware errors.
  • ECAM MMCONF extension to 64-bit addresses, allowing working with larger and more complex PCIe configuration spaces.
  • Initialization of the CRTM (Core Root of Trust for Measurement) in the bootblock, reinforcing the chain of trust from the earliest stages of startup.

Along with this, the following have been introduced optimizations in the calculation of MTRR For AMD platforms, this reduces boot time by simplifying cache configuration, and Glinda's FSP is updated with new versions that improve overall stability.

ACPI and APEI infrastructure for error management

A very important, though less visually appealing, feature is the addition of a Extensive APEI (Advanced Platform Error Interface) infrastructure in ACPI headersComplete structures have been added to support:

  • Sources of error Machine Check Exception (MCE).
  • Errors of Non-Maskable Interrupt (NMI).
  • Reports of PCIe AER (Advanced Error Reporting).

These structures serve as the basis for tables such as BERT (Boot Error Record Table), HEST and EINJ (Error Injection Table)so that platforms can report an accurate picture of hardware errors to the operating system and support "firmware-first" error handling models.

The new types and structures continue the official ACPI specifications and are accompanied by internal validations that ensure that the reported information is consistent and usable by the operating system and diagnostic tools.

Consolidation of commonlib, endianness and memory structures in coreboot 25.12

In the area of ​​common libraries, coreboot 25.12 merges the implementations of coreboot and libpayload endian.h header in commonlibeliminating duplication and ensuring that the entire ecosystem uses the same endianness conversion functions.

As part of this cleanup, the old header and swabXX() functions have been removed, completing the transition to a Standard endianness conversion APIIn addition, memory information structures are enriched with new fields to improve compatibility with SMBIOS type 17 and to report, for example, the voltage of DDR3 modules.

Details of devicetree handling (such as the correct hopping of NOP tokens) are also corrected and it is now stored boot mode information in CBMEMso that the payloads can better coordinate with the firmware in aspects such as normal boot, low battery situations, or charging states.

Other notable improvements to drivers and subsystems that come with coreboot 25.12

Minor but relevant changes This list includes many fixes and improvements with practical impact on real systems:

  • Refactoring of the MediaTek display subsystem, with support for dual DSI and Display Stream Compression (DSC) on MIPI panels, and an enhanced DSI API that passes register structures consistently.
  • Using the Intel Skylake CSE reset state to improve the reliability of restarts.
  • Improvements to the Intel GMA display controller, adding cache and valid cache logic to manage brightness more robustly.
  • Corrections and adjustments to the TPM driver, eliminating duplicate operations and generating cleaner and more accurate ACPI tables.
  • Expanded SPD support, with new DDR4 parts and fixes for dual-chip packages, plus new SMBIOS socket types for BGA1744 packages.
  • Keyboard color configuration options RGB on the EC during startupdesigned for equipment with customizable lighting.
  • In-depth review of the Azalia verb table implementation, improving maintainability and adding timing corrections (e.g., the 521 microsecond delay after disabling RESET#).
  • Generic graphics driver support for devices that are not strictly VGA, expanding the range of supported video hardware.
  • Integration of memory with tags for ARMv9 MTE (Memory Tagging Extension) on MediaTek platforms, adding extra security in memory management.
  • Parallel charging infrastructure for Google Bluey platforms, enabling faster battery charging.
  • USB Type-C support in Qualcomm with PHY configuration and repeaters, as well as SoundWire drivers for Cirrus Logic CS35L56 and CS42L43 codecs.
  • ACPI extensions for RISC-V, gradually expanding support for this emerging architecture.

In the payload ecosystem, libpayload gains features such as Check the physical memory size and compatibility with the legacy LZ4 format. and corrections to ARM64 exception routing, maintaining consistency with commonlib and endian changes.

Toolchains, blobs, and vendor code update

To keep up with the rest of the ecosystem, coreboot 25.12 updates several third-party tools and vendor components. Key toolchain changes include:

  • Binutils update from version 2.44 to 2.45.
  • ACPICA update from release 20250404 to 20250807, incorporating improvements and corrections in the ACPI ecosystem.
  • Removal of the nds32le-elf toolchain from default builds, as it is less relevant in current support.

In vendorcode, the FSP headers are updated Panther Lake (PTL) to FSP 3373_03 and Wildcat Lake (WCL) to 3344_03In addition to applying an FSP update for the AMD Glinda platform, the following submodules are also being developed:

  • 3rdparty/blobs It moves from revision a0726508b8 to 4a8de0324, incorporating 39 commits.
  • 3rdparty/intel-microcode It is updated from 4ded52b4b0 to f9100a225, integrating the latest available microcode fix.

These updates ensure that the firmware built on coreboot 25.12 Take advantage of the latest security, stability, and compatibility fixes offered by silicon suppliers.

Coreboot 25.12 download, verifications, and release cycle

The source code for coreboot 25.12 can be obtained directly from coreboot.org in tar.xz format (and tar.gz, tar.bz2 or zip variants)as well as from mirrors and software archives like Fossies. The version distributed in compressed files includes MD5, SHA1, and SHA256 hashes to verify the download's integrity.

In addition, the launches They sign with PGP/GPG codesTo verify a file, you can use a command like this:

$ gpg –verify coreboot-24.02.01.tar.xz.sig coreboot-24.02.01.tar.xz

If GPG returns a message like “Can't check signature: No public key”, it is enough to retrieve the correct key from the fingerprint Published in the coreboot documentation, run the verification again. It's normal to see warnings about uncertified signatures as trusted: they simply indicate that the user hasn't yet established a chain of trust for those keys.

The fingerprint list includes keys to developers such as Matt DeVillier, Jason Glenesk, Patrick Georgi, Angel Pons, Alexander Couzens or Martin Roth, among others, some of them already expired but maintained for historical purposes.

For those who want to always work with the latest trends, the project reminds us that the ideal is clone the official Git repository directly with:

$ git clone https://review.coreboot.org/coreboot.git

Stable versions, such as 25.12, follow a quarterly publication cycleThe next announced release is 26.03, scheduled for the end of March 2026. Meanwhile, the main branch continues to receive changes and fixes on an ongoing basis.

With all these new features, coreboot 25.12 reinforces its position as A mature alternative to proprietary BIOS, combining support for both new and old hardware, improved debugging and error reporting capabilities, advanced runtime configuration options, and a cleaner, more consistent technical foundation; an update that, while not a visible revolution for everyone, marks an important step for integrators, OEMs, and users who want to take control of what happens before the operating system starts booting.